1. Field of the Invention
The present invention generally relates to computer-implemented methods for simulating reticle layout data, inspecting reticle layout data, and generating a process for inspecting reticle layout data. Certain embodiments relate to a computer-implemented method that includes identifying a first region in reticle layout data that has a printability that is more sensitive to changes in process parameters than a printability of a second region in the reticle layout data.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Designing an integrated circuit (IC) involves creating a schematic design that includes individual devices arranged and coupled to perform a particular function. As ICs become increasingly complex, the design of the ICs also increases in complexity. For example, ICs are generally designed to have smaller dimensions and greater circuit density to improve the speed and other characteristics of the ICs.
The IC design may be developed using any method or system known in the art such as electronic design automation (EDA), computer aided design (CAD), and other IC design software. Such methods and systems may be used to generate the circuit pattern database from the IC design. The circuit pattern database includes data representing a plurality of layouts for various layers of the IC. Data representing the layouts of the various IC layers may be used to determine layouts for a plurality of reticles. Reticles or “masks” are used in a lithography process to transfer a pattern to a resist on a wafer. The terms “reticle” and “mask” are used interchangeably herein.
The layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Typically, these polygons can be generally defined by their size and placement of the reticle. Each reticle is used to fabricate one of the various layers of the IC. The layers of the IC may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
In particular, the reticle is used to pattern a resist in a lithography process step, and then the patterned resist is used to form features of the IC on the wafer. Therefore, the patterned features that are formed on a reticle and are to be transferred to the wafer reflect the characteristics of the features that are included in the IC design. In other words, the features that are formed on the reticle may be based on and are used to form individual components of the ICs such as those described above. The complexity of the IC design, therefore, has a direct impact on the manufacture and inspection of reticles.
Accordingly, as the complexity of the IC design increases, successful reticle manufacture becomes more difficult. For instance, as the dimensions of the IC features and the spacings between the features decrease, the dimensions and spacings of features on the reticle also decrease. In this manner, it becomes more difficult to form these features on a reticle due to, for example, limitations of the reticle manufacturing process. In addition, it becomes more difficult to inspect these features due to limitations of the reticle inspection processes. Furthermore, as is known in the art, the difficulty of successfully reproducing these features on wafers increases as the dimensions and spacings decrease.
Due to the important role that reticles play in semiconductor fabrication, ensuring that the reticles have been manufactured satisfactorily (such that the reticles can be used to produce the desired images on wafers) is critical to successful semiconductor fabrication. In general, during a reticle inspection process, the optical image of the reticle is typically compared to a baseline image. The baseline image is either generated from the circuit pattern data or from an adjacent die on the reticle itself. Either way, the optical image features are analyzed and compared with corresponding features of the baseline image. Each feature difference is then compared against a single threshold value. If the optical image feature varies from the baseline feature by more than the predetermined threshold, a defect may be defined.
Although conventional reticle inspections provide adequate levels of detection accuracy for some applications, other applications require a higher sensitivity or lower threshold value (for identifying defects) while yet other applications require less stringent, higher threshold levels. Since conventional inspections analyze all features of a given type of reticle with the same threshold and analysis algorithm, some features are inspected too stringently while others are not inspected stringently enough.
Electrically critical features of an IC typically include gates of the semiconductor transistor devices. That is, a gate width on the reticle needs to produce a corresponding gate width on the circuit pattern within a relatively small margin of error in order for the fabricated IC device to function properly. If the threshold is set too high, these critical gate areas are not checked adequately enough. Conversely, other features, such as the widths of the interconnections between gate areas, do not affect the function of the IC as much as the gate area width and, thus, do not need to be inspected as stringently as other features. If the threshold is set too low, too many of these non-critical features may be defined as defects such that the inspection results are difficult to interpret and/or computational resources are overloaded.
In sum, therefore, conventional inspection systems waste valuable resources by inspecting regions of the reticle too stringently, and not reliably inspecting other regions stringently enough. In other words, the above described inspection system fails to reliably detect defects within electrically critical areas and inefficiently inspects electrically non-critical regions where somewhat larger defects will not present a problem. Conventional inspection systems and techniques are unable to distinguish between electrically critical and non-critical areas of the reticle. Put in another way, conventional design documentation (e.g., electronic reticle or integrated circuit information) fails to adequately transmit the IC designer's intent regarding the circuit tolerance and resulting IC device dimensions to reticle writer systems, reticle inspection systems, and ultimately wafer inspection systems.
For at least these reasons, some inspection methods have been developed that inspect reticles with varying stringency based on the intent of the IC designer. Examples of such methods are illustrated in U.S. Pat. Nos. 6,529,621 to Glasser et al. and 6,748,103 to Glasser et al., which are incorporated by reference as if fully set forth herein. In this manner, decisions as to the appropriate stringency that should be used to detect defects on reticles can be made based on the electrical significance of features in the reticle layout data.
Such methods have substantially improved the accuracy, meaningfulness, usefulness, and throughput of reticle inspection. However, such methods do not take into account a number of other variables of the reticle layout data that can be used to further increase the value of the reticle inspection. For example, designer intent based inspection methods do not consider the printability of reticle layout data when determining an appropriate stringency for the data. In particular, various characteristics of the reticle layout data such as dimension among others will determine how difficult it will be to accurately print or reproduce the reticle layout data as desired. One way to define the difficulty of accurately printing reticle layout data is by the process window for the reticle layout data (e.g., reticle layout data having a narrow process window will be more difficult to print than reticle layout data having a large process window). As such, it may be desirable to more stringently inspect regions of the reticle layout data that are more difficult to print than regions of the reticle layout data that are less difficult to print. Although some electrically significant areas of an IC may also be difficult to print, currently used reticle inspection methods do not adjust the stringency of the reticle inspection method based on the printability of different regions of the reticle layout data.
Accordingly, it may be advantageous to develop methods that can be used to generate a process for inspecting reticle layout data, to inspect reticle layout data, and/or to simulate reticle layout data while taking into account the printability of various regions of the reticle layout data.